Phase change technology is promising for next generation memories. It uses chalcogenide semiconductors for storing states. The chalcogenide semiconductors, also called phase change materials, have a crystalline state and an amorphous state. In the crystalline state, the phase change materials have a low resistivity, while in the amorphous state they have a high resistivity. The resistivity ratios of the phase change materials in the amorphous and crystalline states are typically greater than 1,000, and thus the resulting memory devices are unlikely to have errors for reading states. The chalcogenide materials are stable at certain temperature ranges in both crystalline and amorphous states and can be switched back and forth between the two states by electric pulses. One type of memory device that uses the principal of phase change in chalcogenide semiconductors is commonly referred to as phase change random access memory (PRAM).
FIG. 1 illustrates a circuit diagram of a conventional phase change memory array, which includes address lines extending in X and Y directions. Each of the memory cells 2 is electrically coupled between one of the address lines extending in the X direction and one of the address lines extending in the Y direction. Memory elements 4 in memory cells 2 are formed of phase change materials. To reduce the disturbance between memory cells, memory cells 2 typically include selectors 6, which may be formed of bipolar transistors, MOS devices, p-n junctions, and the like.
FIG. 2 illustrates a perspective view of a portion of a memory array, which implements the phase change memory array shown in FIG. 1. In this structure, the selectors 6 are formed of p-n diodes, each including a p-type polysilicon layer 8 and an n-type polysilicon layer 10. Phase change elements 4 are stacked on the p-n diodes 6. The p-n diodes 6 are serially connected to a phase change elements 4. Perpendicular address lines are formed overlying and underlying, and are connected to, the memory cells 2. A drawback of the structure shown in FIG. 2 is that the stacked memory cells include several layers, and thus after the step of patterning the memory cell stacks, but before filling the space between the memory cell stacks, the memory cell stacks are prone to collapse.
FIG. 3 illustrates a cross-sectional view of another conventional phase change memory, wherein the cross-sectional view is taken along the word-line direction. The phase change memory includes an N+ word-line 14 formed at the top portion of substrate 12, wherein the N+ word-line 14 is formed by heavily doping the top surface of substrate 12. Memory cells 16 are formed over, and electrically connected to, word-line 14. Each memory cell 16 includes diode selector 21 formed of n-type region 18 and p-type region 20. Bottom electrodes 26, phase change elements 28, and top electrodes 30 are formed over the diode selector 21. Metal lines in the first metallization layer (M1) act as bit-lines. Word-line 14 is further connected to pickup contact 36. Regions 18, 20, 26, and 28 are formed in an inter-layer dielectric (ILD) 22, which may include several sub layers.
The memory array shown in FIG. 3 suffers from drawbacks. First, pickup contact 36 and the underlying word-line 14 form a Schottky contact instead of an Ohm contact, and voltage drop at the Schottky contact results in a higher voltage requirement to the power supply. Second, diodes 21 are formed by forming an opening in ILD 22; performing a silicon ion implantation to form a silicon layer in the opening; and then growing silicon in the opening using solid phase epitaxy. Disadvantageously, this process is performed after the formation of peripheral MOS devices, and hence causing a dilemma, that is, a low epitaxy temperature will reduce the growth rate, and hence reducing the manufacturing throughput. On the other hand, a high epitaxy temperature will increase the thermal budget of the already formed peripheral MOS devices, adversely affecting their performance. Third, the silicon ion implantation requires a high dosage and a high energy, which will also adversely affect the performance of the peripheral MOS devices. New memory cells free from the above-discussed problems are thus needed.